Advanced Packaging (CoWoS / SoIC)

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TSMC
TSMC

Overview

TSMC's 2.5D and 3D packaging technologies that integrate GPU dies with stacks of high-bandwidth memory on silicon interposers - the technology every leading AI accelerator depends on, and for two years the binding constraint on global AI chip supply. Capacity is being expanded roughly fourfold from late-2024 levels, including the new AP7 plant in Chiayi and two planned Arizona packaging facilities.

Aggressive expansion toward ~130-140k CoWoS wafers/month by end of 2026, up from ~35k in late 2024 (10–20% of the 2026 capital budget); as of August 2026, TSMC is also outsourcing the CoW front-end step to OSAT partners (ASE and others) to ease capacity pressure driven largely by Nvidia's reservation of an estimated 800,000-850,000 CoWoS wafers for 2026

Key Specs

CoWoS capacity target

~130-140k wafers/month by late 2026 (~4x late-2024)

Share of 2026 capex

10–20% of $60–64B

5.5-reticle CoWoS-L yield

98-99% in volume production across multiple AI customer products (Aug 2026); memory and ABF substrates flagged as the next AI-supply bottleneck, not CoWoS itself

2027 allocation shift

Reported (Aug 26, 2026) to reallocate share toward AMD (agentic-AI processor demand, MI355/MI400) and trim Nvidia's share as TSMC's expanding CoWoS capacity outgrows any single customer's 2026 lock-in; Nvidia still holds an estimated ~60% of 2026 CoWoS capacity (~595k wafers)