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TSMC

SPublicFounded 1987🇹🇼Hsinchu, Taiwan
CEO

C.C. Wei (Chairman & CEO)

Data verified as of Jul 19, 2026

Summary

Taiwan Semiconductor Manufacturing Company, founded in Hsinchu in 1987 by Morris Chang, invented the dedicated-foundry business model and now dominates it utterly: 69.9% of the global foundry market in 2025, rising to 72.3% in Q1 2026, with Samsung a distant second at 6.5%. It is effectively the sole manufacturer of leading-edge AI silicon — Nvidia, Apple, AMD, and Broadcom all fab their flagship chips there — which made it the primary beneficiary of the AI buildout: 2025 revenue hit a record $122.4B (+35.9%), and Q1 2026 revenue grew another 35.1% to $35.9B at a 66.2% gross margin, with high-performance computing now 61% of sales. Its N2 (2nm) node, the company's first gate-all-around process, entered volume production on schedule in Q4 2025 at Fab 22 in Kaohsiung, with the enhanced N2P variant due in H2 2026 and the A16 node (backside power delivery) now slated for 2027 after slipping from late 2026. TSMC raised its 2026 capex guidance to a record $60–64B in July 2026 — the largest capital budget in semiconductor history — while globalizing its footprint: Arizona's Fab 21 has produced 4nm chips at Taiwan-par yields since Q4 2024, and on its July 16 earnings call TSMC pledged roughly $100B more to expand the Arizona campus with at least four additional 2nm-and-below fabs, lifting its total US commitment to about $265B (the largest foreign direct investment in US history); Japan's JASM is building a second Kumamoto fab upgraded to 3nm for late 2027, and the Dresden ESMC fab targets production in late 2027. A January 2026 US–Taiwan trade deal exempts TSMC from new 25% Section 232 semiconductor tariffs in proportion to its US buildout. The overhang remains geopolitical: the vast majority of its leading-edge capacity sits on Taiwan, at the center of US–China tension.

Company OverviewRead the long-form profile of TSMC

Main Products

N2 Process Node

TSMC's 2nm-class node and its first with gate-all-around nanosheet transistors, delivering 10–15% more speed or 25–30% less power than N3E. Volume production began on schedule in Q4 2025 at Fab 22 (Kaohsiung) and Fab 20 (Hsinchu), with the enhanced N2P variant following in H2 2026 — the process powering the next generation of flagship smartphone and AI silicon.

In volume production since Q4 2025 with reported yields around 70%; ramping through 2026 on smartphone and HPC demand, N2P due H2 2026

Volume production startQ4 2025 (on schedule)
Performance vs N3E10–15% speed gain or 25–30% power reduction
Reported yield~70% (early 2026)

TSMC's 2.5D and 3D packaging technologies that integrate GPU dies with stacks of high-bandwidth memory on silicon interposers — the technology every leading AI accelerator depends on, and for two years the binding constraint on global AI chip supply. Capacity is being expanded roughly fourfold from late-2024 levels, including the new AP7 plant in Chiayi and two planned Arizona packaging facilities.

Aggressive expansion toward ~130k CoWoS wafers/month by end of 2026, up from ~35k in late 2024; 10–20% of the 2026 capital budget

CoWoS capacity target~130k wafers/month by late 2026 (~4x late-2024)
Share of 2026 capex10–20% of $60–64B
Arizona Gigafab Cluster (Fab 21)

TSMC's US manufacturing site in Phoenix, now backed by a ~$265B commitment — the largest foreign direct investment in US history — after TSMC pledged another ~$100B on its July 16, 2026 earnings call to add at least four more 2nm-and-below fabs. Phase 1 has produced 4nm chips at Taiwan-par yields since Q4 2024 for customers including Apple and Nvidia; Phase 2 brings 3nm production in 2027 (pulled in about a year, equipment move-in from Q3 2026); Phase 3, targeting N2 and A16, has broken ground for ~2029. TSMC expects ~30% of its 2nm-and-below capacity to eventually sit in the US.

Phase 1 in N4 volume production since Q4 2024; Phase 2 (N3) equipment move-in from Q3 2026, production 2027; Phase 3 (N2/A16) targeting ~2029; four more fabs pledged Jul 2026

Total US commitment~$265B (raised another ~$100B on Jul 16, 2026)
Phase 1 productionN4 (4nm) since Q4 2024, yields on par with Taiwan
Phase 2 production targetN3 in 2027 (pulled in ~1 year)

A16 Process Node

In Development

TSMC's 1.6nm-class node combining gate-all-around nanosheets with Super Power Rail backside power delivery, targeting AI and HPC chips with 8–10% more speed or 15–20% less power than N2P. Volume production is now slated for 2027 after slipping from the original H2 2026 target; the follow-on A14, A12, and A13 nodes extend the roadmap to 2029 — all planned without High-NA EUV.

Volume production 2027 (slipped from H2 2026 at the April 2026 Technology Symposium)

Performance vs N2P8–10% speed gain or 15–20% power reduction
Volume production target2027

What's Next

N2P volume production

The enhanced 2nm node enters volume production, offering a performance/power step over N2 for the 2027 flagship chip generation while N2 itself ramps through Taiwan's Fab 22 and Fab 20.

H2 2026

Arizona Fab 21 Phase 2 begins 3nm production

The most advanced node yet manufactured in the US: construction finished months ahead of schedule, equipment move-in starts Q3 2026, and volume N3 production is targeted for 2027 — pulled in roughly a year from the original plan.

2027

A16 volume production

TSMC's first node with Super Power Rail backside power delivery enters volume production, now targeted for 2027 after the April 2026 roadmap update moved it from H2 2026. Watch whether AI/HPC lead customers (the node's explicit target market) land on schedule.

2027

Dresden ESMC fab starts production

TSMC's €10B+ European joint venture with Bosch, Infineon, and NXP (TSMC 70%) finished structural construction in late 2025; equipment move-in runs through H2 2026 with production of 28/22nm and 16/12nm automotive-class chips targeted for late 2027 at 40k wafers/month.

Late 2027

JASM Kumamoto Fab 2 operations — upgraded to 3nm

Japan's second TSMC fab, under construction since October 2025 (~$13.9B), was upgraded in February 2026 from the originally planned 6/7nm to 3nm — which would give Japan its first leading-edge node when operations begin around the end of 2027.

Late 2027

Track Record

1 of 3 announced dates hit · 2 slipped

A16 volume production in H2 2026

Target H2 2026 · Resolved Apr 23, 2026

Announced in April 2024 for production in 2026, A16 was pushed to 2027 in the roadmap TSMC presented at its April 2026 North America Technology Symposium — the company's most visible recent node slip.

Slipped

N2 (2nm) volume production in H2 2025

Target H2 2025 · Resolved Dec 30, 2025

N2 entered volume production in Q4 2025 exactly as promised, confirmed December 30, 2025 — TSMC's first gate-all-around node, ramping at Fab 22 Kaohsiung and Fab 20 Hsinchu with reported yields around 70%.

Hit

Start construction of Kumamoto Fab 2 by end of 2024

Target End of 2024 · Resolved Oct 28, 2025

Construction was promised for end-2024 but began only in late October 2025, roughly ten months late, after local traffic and infrastructure concerns; the end-2027 operations target was retained and the planned process later upgraded to 3nm.

Slipped

Recent News

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Operations & Revenue

StatusOperational — record growth on AI demand

Record run continues: Q2 2026 net profit jumped 77% YoY to a record NT$706.6B (~US$22B) on record revenue of NT$1.27T (+36% YoY), TSMC's fifth straight record quarter, with advanced CoWoS packaging reported sold out through year-end. Management is steering 2026 capex toward the top of the $52–56B range on AI demand. TSMC is effectively the sole manufacturer of leading-edge AI silicon — Nvidia, Apple, AMD, Broadcom, and now Intel as a foundry customer — holding ~72% of foundry revenue. Key risks: extreme geographic concentration in Taiwan amid China tension; US tariff policy (a January 2026 Section 232 25% tariff on advanced logic, mitigated by the US–Taiwan deal's quota exemptions tied to the $165B US buildout); margin dilution from overseas fabs; and any AI-capex correction, which CEO C.C. Wei has publicly dismissed while pledging disciplined investment.

Revenue Streams

High-performance computing (AI accelerators & data center)

Fabricating GPUs, AI accelerators, and server CPUs for Nvidia, AMD, Broadcom, and hyperscaler custom-silicon programs — 61% of Q1 2026 revenue and growing 20% quarter-over-quarter, the dominant and fastest-growing stream.

Smartphone SoCs

Application processors and modems for Apple and other handset makers — 26% of Q1 2026 revenue, historically TSMC's largest segment before AI overtook it.

IoT, automotive & consumer electronics

Specialty and mature-node chips for IoT devices (6% of Q1 2026 revenue), automotive (4%), and digital consumer electronics (1%), largely from 8-inch fabs and the Japan/China sites.

Advanced packaging (CoWoS / SoIC)

2.5D/3D packaging that assembles GPU dies with high-bandwidth memory — the binding constraint on AI accelerator supply. Capacity is being quadrupled toward ~130k wafers/month by late 2026, absorbing 10–20% of the 2026 capital budget.

Key Metrics

Employees

90,557 (as of Dec 31, 2025)

Est. Annual Revenue

$122.42B (FY2025, +35.9% YoY; net income $55.21B)

Foundry market share

72.3% (Q1 2026; 69.9% FY2025)

Latest quarterly revenue

NT$1.27T / ~US$40B (Q2 2026, +36% YoY); net profit NT$706.6B (+77% YoY, record)

H1 2026 revenue

NT$2.40T (+35.6% YoY); June NT$442.68B (+67.9% YoY, +6.2% MoM)

Market cap

~$2.25T (Jul 2026)

2026 capex guidance

$60–64B (raised from $52–56B on Jul 16, 2026)

Gross margin

66.2% (Q1 2026)

Advanced-node share of wafer revenue

74% from ≤7nm (FY2025); 3nm alone 25% (Q1 2026)

Fabs

18 (incl. six 12-inch GIGAFABs); >17M 12-inch-equivalent wafers/yr

Customers / products (2025)

534 customers, 12,682 distinct products

Timeline

2026Record FY2025 results and history's largest chip capex budget

On January 15, 2026, TSMC reports record 2025 revenue of $122.42B (+35.9%) with net income up 51.2%, and guides 2026 capex to $52–56B — the largest single-year capital budget in semiconductor history. The same day, a US–Taiwan trade deal exempts US-investing Taiwanese chipmakers from new Section 232 tariffs.

2026Roadmap through 2029 unveiled; A16 slips to 2027

At the April 2026 North America Technology Symposium, TSMC lays out N2P and A16 (now 2027, from H2 2026), A14 next, and A12/A13 for 2029 — notably planned without ASML's High-NA EUV tools.

2026Q2 2026 profit jumps 77% to a fifth straight record quarter

On July 16, 2026, TSMC reports second-quarter net profit of NT$706.6 billion (about US$22B), up 77% YoY to a record and far above the ~NT$632.6B analyst consensus, on record revenue of NT$1.27 trillion (+36% YoY). Demand for leading-edge N3/N5 nodes and advanced CoWoS packaging — reported sold out through year-end — kept capacity near full as the AI buildout continued.

2026Pledges ~$100B more for Arizona; raises 2026 capex to $60–64B

On its July 16, 2026 earnings call, TSMC said it will invest roughly $100B more to expand its Arizona campus with at least four additional fabs for 2nm-and-below nodes, lifting its total planned US investment to about $265B — the largest foreign direct investment in US history. It also raised 2026 capital-spending guidance to a record $60–64B (from $52–56B), with 70–80% earmarked for advanced process technology, and expects ~30% of its 2nm-and-below capacity to eventually sit in the US.

2025$100B additional US investment announced ($165B total)

On March 4, 2025, TSMC announces three more fabs, two advanced-packaging plants, and an R&D center in Arizona, lifting its total US commitment to $165B — the largest foreign direct investment in US history.

2025N2 (2nm) enters volume production on schedule

TSMC's first gate-all-around nanosheet node enters volume production in Q4 2025 at Fab 22 (Kaohsiung) and Fab 20 (Hsinchu), confirmed December 30, 2025 — with reported yields around 70% and a claimed 10–15% speed gain or 25–30% power cut versus N3E.

2024JASM Fab 1 opens in Kumamoto, Japan

TSMC's Japanese joint venture with Sony, Denso, and Toyota opens its first fab in February 2024, producing 12–28nm chips — the anchor of Japan's semiconductor revival.

2024Arizona Fab 21 enters volume production

Phase 1 of Fab 21 begins high-volume 4nm (N4) production in Q4 2024 — TSMC's first US leading-edge output, with yields on par with Taiwan fabs and customers including Apple and Nvidia.

20223nm (N3) volume production begins in Tainan

TSMC starts volume production of N3, the industry's most advanced node, extending its leadership through the generation that would power the first wave of AI accelerators.

20205nm production begins; Arizona fab announced

Volume production of 5nm chips begins (Apple's A14 and M1 era), and TSMC announces its first US leading-edge fab in Phoenix, Arizona, with an initial $12B commitment.

2018Takes process leadership with 7nm; C.C. Wei becomes CEO

TSMC becomes the first to high-volume 7nm production, seizing process leadership from Intel — a lead it has never relinquished. C.C. Wei becomes CEO the same year.

1994Lists on the Taiwan Stock Exchange

TSMC lists on the TWSE under ticker 2330, followed in 1997 by NYSE ADRs (TSM) — the first Taiwanese company to list on the NYSE.

1987Morris Chang founds the world's first pure-play foundry

TSMC is founded in Hsinchu with Taiwan's government providing 48.3% of the capital and Philips 27.6% ($58M) — the first semiconductor company to manufacture only other companies' chip designs, the business model that reshaped the industry.

Funding

RoundDateAmountInvestorsSource
Founding capital1987Taiwan government 48.3%, Philips $58M (27.6%)Government of Taiwan, Philips, private Taiwanese companies (~20%)
TWSE listing1994IPOPublic markets (TWSE: 2330)
NYSE ADR listingOct 1997ADR listingPublic markets (NYSE: TSM) — first Taiwanese company on the NYSE