WSE-3 Turbo
Active
Cerebras Systems
Overview
Current flagship wafer-scale processor inside CS-4. Same 4 trillion transistors, 900,000 cores, 46,225 mm2, and 44 GB of SRAM as WSE-3, clocked and packaged for roughly 2x the speed of the prior wafer, 250 PFLOPs of AI compute, and 43.2 PB/s of memory bandwidth per wafer. Redundant cores and fail-in-place routing are how Cerebras yields a dinner-plate-sized die.
Announced with CS-4 on August 18, 2026. Ships as the compute element of CS-4; WSE-3 (non-Turbo) remains in CS-3 production. Fabbed at TSMC without HBM, CoWoS, or 3nm.